1. Field of the Invention
The present invention relates in general to pipelined analog-to-digital converters (ADCs), and in particular to a pipelined ADC having a dual supply voltage.
2. Description of Related Art
A typical digital communication transmitter encodes a data sequence to produce a waveform data sequence defining an analog signal. The transmitter then converts the waveform data sequence into the analog signal and transmits it to a receiver. An analog-to-digital converter (ADC) within the receiver periodically digitizes the analog signal to produce a waveform data sequence representing successive voltage levels of the analog signal. Digital signal processing circuits then process the waveform data sequence to recover the original data sequence. In a digital communication system operating at high data rates, the receiver must employ a high resolution ADC that can sample the analog signal at a high frequency. For example, a very high speed broadband access digital subscriber loop (VDSL) offering downstream data rates up to 52 Mbps needs an ADC providing 12 effective bits of resolution at a sample rate of 35 MHZ.
A pipelined ADC employing a sequence of low-resolution ADC stages to digitize an analog signal with high resolution is well suited for high-speed, high-resolution applications. The following U.S. patents incorporated herein by reference describe various pipelined ADC architectures:
U.S. Pat. No. 6,169,502, issued Jan. 2, 2001 to Johnson et al.,
U.S. Pat. No. 6,366,230, issued Apr. 2, 2002 to Zhang et al., and
U.S. Pat. No. 6,456,223, issued Sep. 24, 2002 to Yu et al.
FIG. 1 illustrates a typical prior art pipelined ADC 10 including a set of N ADC stages 12(1)-12(N) and a set of Nxe2x88x921 shift registers 14(1)-(Nxe2x88x921). A differential analog signal A(1) to be digitized is applied as input to the first stage 12(1). In response to each nth leading (or trailing) edge of a clock signal (CLOCK), each ith stage 12(i) samples the voltage of its analog input signal A(i) and produces a B-bit data word xi(n) approximating the magnitude of the sampled input signal voltage with B-bit resolution. Each ith stage 12(i) other than the last stage 12(N) also supplies an output differential analog residue signal A(i+1) as an input signal to the next stage 12(i+1) wherein
A(i+1)=2B[A(i)xe2x88x92(VMAX/2B)(xi(n)xe2x88x922Bxe2x88x921 +xc2xd)]
where VMAX is the peak-to-pak full range voltage of the stage""s differential input signal A(i). The output residue signal A(i+1) of each ith stage 12(i) is thus proportional to the error difference between the sampled voltage of its input signal A(i) and the voltage level represented by the stage output data xi(n).
For example a pipelined DAC for which B=2, VMAX=5 volts, and N=3 stages could digitize an input signal A(1) ranging from xe2x88x922.5V to 2.5V with BxN=6-bit resolution. With B=2, each ith data word xi(n) can have any of four 2-bit values representing xe2x88x921.875, xe2x88x920.625 or 1.875 volts. Thus when A(1) is, for example, 0.4 volts when sampled on an nth CLOCK signal pulse, the first stage output data is
x1(n)=10(binary)
representing a magnitude of 0.625 volts which approximates the actual 0.4 volt magnitude of the A(1) signal. The stage 1 output residue signal A(2) will be
A(2)=22[0.4xe2x88x92({fraction (5/4)})(2xe2x88x921.5)]=22 [0.4xe2x88x920.625]=xe2x88x920.9 volts
On the (n+1)th CLOCK signal edge, second stage 12(2) will digitize the xe2x88x920.9 volt A(2) signal to produce output data
x2(nxe2x88x921)=01(binary)
corresponding to a magnitude of xe2x88x920.625 volts approximating the xe2x88x920.9 volt A(2) signal. The second state output analog signal A(3) has magnitude
A(3)=22[xe2x88x920.9xe2x88x92({fraction (5/4)})(1xe2x88x921.5)]=22 [xe2x88x920.9+0.625]=xe2x88x921.1 volts.
On the (n+2)th CLOCK signal edge, the final pipeline stage 12(3) will digitize the 1.4 volt A(3) signal to produce output data
x3(n+2)=01(binary)
corresponding to a measured value of xe2x88x920.625 volts.
Successive stages 12(1)-12(N) produce their output data x1(n)-xN(n) with progressively larger delays. Therefore shift registers 14(1)-14(Nxe2x88x921) delay successive stage output data by progressively decreasing delays so that they concurrently produce output data x1(nxe2x88x92N+1)-xN(n) that can be combined to form a single NxB-bit OUTPUT word representing the magnitude of the A(1) input signal when sampled by stage 12(1) N CLOCK signal cycles earlier. In the example case the ADC""s digital OUTPUT word value will be
OUTPUT={X3(n), X2(nxe2x88x92N+2), X1(nxe2x88x92N+1)}=100101(binary) =37(decimal)
The OUTPUT word value, which can range from 0 to 26xe2x88x921, represents the sampled magnitude of input signal A(1) with 6-bit resolution. In this example the OUTPUT word represents an input signal voltage
A(1)=(VMAX/26)xc3x97(OUTPUTxe2x88x9225+xc2xd) =({fraction (5/64)})5.5 =0.429 volts
which is as close to the actual 0.4 volts of ADC input signal A(1) as can be represented given a xe2x88x922.5 to 2.5 volt range and 6-bit resolution.
FIG. 2 illustrates an example architecture for stage 12(1) of the pipelined ADC of FIG. 1. Stages 12(2)-12(Nxe2x88x921) are similar. An amplifier 24 amplifies the differential A(1) signal to produce sample voltage Axe2x80x2 (1). A sample and hold (S/H) circuit 16 samples and holds Axe2x80x2 (1) on each leading or trailing edge of the CLOCK signal and the sample voltage Axe2x80x2 (1) stored in SandH circuit 16 is supplied to a B-bit ADC 18. ADC digitizes Axe2x80x2 (1) to produce B-bit output data x1(n). A B-bit digital-to-analog converter (ADC) 20 converts x1(n) into an offset voltage
VOFF=(VMAX/2B)(x1(n)xe2x88x922Bxe2x88x921+xc2xd).
An analog summing amplifier 22 offsets Axe2x80x2 (1) by VOFF to produce the differential stage output residue signal A(2).
FIG. 3 depicts an example of final stage 12(N) of FIG. 1 that is similar to stage 12(1) of FIG. 2 except that it omits DAC and summing amplifier 22.
Error Sources
Various factors can compromise the accuracy of the pipelined ADC 10 of FIGS. 1-3 including, for example:
1. thermal noise,
2. comparator offset error within the ADC 18 of any stage,
3. error in the gain of amplifier 24 of any stage,
4. nonlinearity of ADC 18,
5. nonlinearity of DAC 20,
6. nonlinearity of amplifier 24, and
7. incomplete settling of output residue signal A(2).
Among the above sources of error, only thermal noise is random and varies from sample-to-sample. The other sources of error, mainly mismatches in circuit elements such as transistor dimensions, resistor and capacitor values, are xe2x80x9csystematicxe2x80x9d in that they are consistent from sample-to-sample. Many correction and calibration techniques are available to significantly improve the accuracy of ADCs by compensating for systematic errors. For example it is possible to substantially reduce systematic errors by adjusting the gain and offset of the amplifier 24 in one or more stages. Thus the accuracy of modern pipelined ADCs is typically limited by thermal noise rather than by systematic errors.
In response to each leading or trailing edge of the CLOCK signal, SandH circuit 16 briefly connects the sample voltage Axe2x80x2 (1) signal to an internal capacitor so that amplifier 24 producing the Axe2x80x2 (1) signal can charge the capacitor to the current Axe2x80x2 (1) signal voltage. The capacitor voltage remains at the sampled signal Axe2x80x2 (1) voltage for the remainder of the CLOCK cycle to allow the A(2) and X1(n) stage outputs time to settle to new levels.
The sampling capacitor actually remains only approximately at the sampled signal Axe2x80x2 (1) voltage during the remainder of the CLOCK cycle because thermal noise tends to make the sample voltage Axe2x80x2 (1) vary with time. In a pipelined ADC properly calibrated to compensate for systematic error, the variation in sample voltage Axe2x80x2 (1) due to thermal noise can be the most significant source of error in the ADC""s output data. Circuit designers often refer to this source of thermal noise as xe2x80x9cKT/C noisexe2x80x9d because the thermal noise power in the Axe2x80x2 (1) signal is proportional to KT/C, where K is the Boltzmann""s constant (1.38xc3x9710xe2x88x9223 Joules/xc2x0 K.), where T is the temperature of the SandH circuit in degrees Kelvin, and where C is the capacitance of the sampling capacitor.
Since thermal noise is proportional to KT/C, we can decrease thermal noise power in any ADC stage by increasing the magnitude of the sampling capacitance C within SandH circuit 16. But increasing C also has undesirable effects. When SandH circuit 16 is to sample the Axe2x80x2 (1) signal at a high frequency, amplifier 24 must be able to charge it quickly. When we increase sampling capacitance C, amplifier 24 needs more time to charge the sampling capacitance thereby reducing the maximum sampling frequency at which the SandH circuit can operate.
One way to compensate for the reduction in sampling frequency resulting from an increase in sampling capacitance is to increase the ability of the charging amplifier 24 to supply more charging current to the sampling capacitance so that it can charge it more quickly. The charging amplifier 24 includes one or more output transistors for coupling the sampling capacitor to a voltage source VDD when briefly turned on at the start of each CLOCK signal cycle. Since the impedance of those transistors limits the magnitude of the current, we can increase the amount of charging current amplifier 24 supplies to the sampling capacitor by increasing the number of its output transistors and/or by increasing the channel widths of its output transistors, thereby reducing transistor impedance. Thus when it is necessary to increase the size of the sampling capacitor in any stage 12(1)-12(N) to reduce thermal noise power, designers know to also increase the number or channel widths of output transistors in the amplifier 24 supplying current to the sampling capacitor to avoid reducing the ADC""s maximum allowable sampling frequency.
But when we increase the number and/or channel widths of transistors in an ADC stage, we also increase the area of an IC die occupied by that stage as well as the stage""s power consumption.
Tapered Pipelined ADCs
Since the output data xi(n) generated by each stage provides less significant bits of the ADC OUTPUT word than its preceding stage, an error in output data of each successive stage has a lower impact on the accuracy of the ADC OUTPUT word than an error in the output data of its preceding stage. For example consider a pipelined ADC having N=3 stages, having B=4 bit resolution per stage, and having a differential input signal voltage ranging from xe2x88x92VMAX/2 to +VMAX/2 volts, wherein thermal noise in each stage can be sufficiently large to occasionally cause an error in the least significant bit in the stage data output. Since the resolution of the first stage is VMAX/16, thermal noise in the first stage output data can cause the value of the pipelined ADC OUTPUT word to vary by as much as VMAX/16. Since the resolution of the second stage is VMAX/256, the thermal noise error in the second stage output data can cause the OUTPUT word of the pipelined ADC to vary only by a maximum of VMAX/256. A 1-bit thermal noise error in the third stage output data can cause the OUTPUT word of the pipelined ADC to vary only by as much as VMAX/4096. Thus while increasing the sampling capacitance of the SandH circuit of the first stage of a pipelined ADC can greatly reduce the error in the ADC""s OUTPUT word arising from thermal noise, increasing sampling capacitance of subsequent stages reduces thermal noise error by progressively smaller amounts.
Accordingly successive stages of many pipelined ADCs employ progressively smaller sampling capacitors requiring amplifiers of progressively lower current output to supply them with charging current. Since amplifiers capable of providing smaller charging currents require less floor space than amplifiers capable of producing larger charging currents, successive stages of such a xe2x80x9ctaperedxe2x80x9d pipelined ADC occupy progressively smaller floor space as illustrated in FIG. 4. They also consume progressively smaller amounts of power.
CMOS Device Scalability
Complementary Metal Oxide Semiconductor (CMOS) technology has dominated the semiconductor industry for decades due mainly to two characteristics of CMOS devices: zero static power dissipation, and scalability. A zero static power dissipation device dissipates very little power except when it changes state. In a digital circuit employing synchronous logic, state changes occur only at the start of each clock cycle, and a CMOS IC therefore has a relatively low average power consumption rate compared to most other types of ICs.
The xe2x80x9cscalabilityxe2x80x9d of CMOS devices relates to the fact that we can make CMOS devices forming a circuit smaller without changing the basic function of the circuit. If we reduce the dimensions (width, length, and thickness) of a CMOS transistor by xcex1%, and if we also reduce the supply voltage, threshold voltage and doping levels by xcex1%, then the current through the transistors and its capacitance will be reduced by xcex1%, though the electric field characteristics within the transistor will remain unchanged. The switching speed of a CMOS inverter, a fundamental building block of CMOS logic, is proportional to I/CV, where I is the current, C is the channel capacitance of the transistors forming the inverter, and V is the inverter""s supply voltage. When we scale down the channel dimensions and doping levels of transistors forming a CMOS inverter, for example by 50%, we reduce I, C and V each by 50%, thereby doubling the speed of the inverter and allowing it to operate at twice the frequency. Also since current and voltage levels are each reduced by 50%, the CMOS device""s power consumption, which is proportional to the product of its current and voltage levels, is reduced by a factor of four. Thus by scaling down a CMOS device we allow it to achieve higher device density and speed while dissipating substantially less power. In the past decade, CMOS technology has been scaled down from minimum channel lengths of 0.5 xcexcm to 0.13 xcexcm, resulting in a supply voltage reduction from 5V to 1.2V and in increased performance and decreased costs.
While scaling down CMOS devices has many advantages with respect to digital circuits, it may have some distinct disadvantages with respect to analog circuits. When we reduce the supply voltage of an analog circuit to accommodate scaled down transistor dimensions, we limit the maximum allowable voltage swing of the analog signal the circuit can process, and that has an adverse effect of the circuit""s dynamic range. xe2x80x9cDynamic rangexe2x80x9d is a commonly employed figure of merit for an analog circuit representing a ratio between the highest signal voltage signal that the circuit can handle and the smallest signal voltage that the circuit can resolve. A circuit""s supply voltage limits the highest signal voltage an analog circuit can handle and thermal noise limits the lowest signal voltage an analog circuit can resolve. When we scale down the transistors forming an analog circuit by xcex1%, thereby decreasing its supply voltage by xcex1%, then the amplitude of the highest signal voltage it can handle is reduced by xcex1%. But since thermal noise remains unchanged, the amplitude of the lowest signal voltage the circuit can resolve remains unchanged. The circuit""s dynamic range is therefore reduced by xcex1%.
Therefore to avoid a reduction in a circuit""s dynamic range after scaling down an ADC pipeline design, a designer reduces thermal noise power by increasing sampling capacitance, and then increases the size and/or number of transistors in the charging amplifiers the stages to avoid a reduction in operating frequency. However, in general for pipelined ADC stages of comparable dynamic range and operating frequency, power consumption and floor space is lower for ADC""s implemented by transistors having longer channel lengths operating at a higher supply voltages than for ADC""s implemented by transistors having shorter channel lengths operating at a lower supply voltages because ADCs operating at the lower voltages need more transistors and larger capacitors. Thus while scaling down transistors in a digital circuit can decrease floor space and power consumption, scaling down transistors in an analog circuit such as a pipelined ADC can increase power consumption and floor space when the circuit""s level of performance is to be preserved.
When an IC such as an ADC converter includes both analog and digital circuits, the disadvantages of scaling down and IC""s analog circuits to some extent offsets the advantages of scaling down the IC""s digital circuits. One approach to maintaining analog circuit performance when digital circuits are scaled down is to implement the analog and digital circuits in separate ICs so that the analog circuits need not be scaled down with the digital circuits. But this solution increases board size, package size, bill of material costs, and parts count. Since the advantages of scaling digital circuits are so overwhelming, and since the advantages of integrating both digital and analog circuits in the same chip are compelling, with further reductions in CMOS channel widths on the horizon, circuit designers will find maintaining analog circuit performance will be a continuing challenge.
The invention relates to a pipelined analog-to-digital converter (ADC) for processing an analog input signal to produce a sequence of digital output word (OUTPUT) representing successive magnitudes of the input signal sampled in response to successive leading (or trailing) edges of a clock signal.
The ADC includes a set of N stages connected in series to form a pipeline wherein a first stage of the pipeline receives the analog input signal as its stage input signal, and wherein each of the first Nxe2x88x921 stages of the pipeline generates and supplies an analog residue signal as an input signal to a next succeeding stage of the pipeline. Each stage includes an amplifier for amplifying the stage input signal to produce a sample voltage and includes a sample and hold circuit for charging its sampling capacitance to the sample voltage in response to each of a succession of clock signal edges. Each stage also includes a low resolution DAC for producing digital stage output data representing an approximate magnitude of the sample voltage, and circuits for driving the stage""s analog output residue signal to a voltage proportional to a difference between the magnitudes of the sample voltage and that stage""s output data. Shift registers delay the output data of each stage by an appropriate number of clock cycles so that the output data of all stages can combine to form a succession of high resolution digital representations of successive samples of their analog input signal voltage.
All pipeline stages are implemented within a single integrated circuit, but the charging amplifiers within the first M stages operate with a higher supply voltage than charging amplifiers within the last N-M stages and employ transistors having larger minimum channel lengths capable of operating at the larger supply voltage. For example the amplifiers in the first M stages could be implemented using 0.35 xcexcm technology CMOS transistors capable of operating at 3.3 V while amplifiers in the last N-M stages could be implemented employing either 0.13 xcexcm or 0.18 xcexcm technology CMOS transistors operating at 1.2V or 1.8V, respectively.
The higher supply voltages of the charging amplifiers of the first M stages allow them to charge the stage""s sampling capacitance over a wider voltage range. The thermal noise power of a stage is a function of the stage""s sampling capacitance and is independent of the charging voltage, so increasing the range of a stage""s charging voltage does not reduce the thermal noise power generated in the stage""s sampling capacitance. But increasing the range of the charging voltage reduces the effects of a given level of thermal noise power on the stage""s output data by making thermal noise a smaller percentage of the sample voltage. Thus increasing supply voltage in the first M stages to permit increased sample voltage range decreases the effects of thermal noise on the output data those stages.
Although the first M stages must employ transistors having larger minimum channel lengths to accommodate the increased supply voltage, the total amount of IC die area occupied by each of the first M stages and the amount of power they consume is less than would be required were the first M stages to employ the same lower supply voltages and smaller channel length transistors as the last N-M stages, since more transistors and larger capacitors would be needed to achieve a similar level of noise immunity. The charging amplifiers in last N-M stages of the pipeline can operate at a lower supply voltage because with thermal noise power in those stages having a lesser effect on digitization accuracy, it is preferable in terms in terms of minimizing stage size and power consumption to employ smaller channel length transistors operating at the lower supply voltage.
While a CMOS IC implementing a pipelined ADC in accordance with the invention requires two different power supply voltages and two different CMOS transistor technology sizes, many CMOS manufacturing processes currently permit this. For example IC manufacturing processes implementing either 0.13 xcexcm CMOS technology or 0.18 xcexcm CMOS technology ICs typically permit the same ICs to also include 0.35 xcexcm technology CMOS transistors in their I/O circuits operating at higher supply voltages to allow the ICs to communicate with external circuits through higher voltage signals. Thus since many ICs already incorporate two CMOS technologies and require two different supply voltages, the invention can be implemented without requiring any changes to currently available IC manufacturing processes and without increasing the number of different supply voltages such ICs already require.
The value of M, the number of stages employing the larger transistors and higher supply voltage, is a matter of design choice and is suitably selected to minimize a weighted combination of total power consumption and circuit area needed to provide a desired level of thermal noise immunity.